Quantitative analysis of vector code

In this paper we present the results of a detailed simulation study of the execution of vector programs on a single processor of a Convex C3480 machine, using a subset of the Perfect Club benchmarks. We are interested in evaluating several cost/performance tradeoos that the machine designers made in order to asses which features of the architecture severely limit the performance attainable. We present the detailed usage of the vector functional units and a study of the kinds of resource connicts that stall the machine. The results obtained show that the resources of the vector architecture are not eeciently used mainly due to the single bus memory architecture. Other severe limitations of the machine turn out to be the lack of chaining between vector loads and vector computations, and the lack of a second general purpose functional unit. We also present some data about the port pressure on the vector register le and we see that stalls due to port connicts are relatively high. We also consider the slowdown introduced by spill code and nd that the limited number of vector registers also limits performance.